Any logic function may be performed by combining logic gates. Logic gates include those that perform a logical function such as OR, AND, NOR, NAND, INVERT, and other functions. All logic functions may be implemented with only NAND gates. Logic gates may be implemented in a variety of ways using transistors, both bipolar and MOSFETs, diodes, and resistors.
A prior art NAND gate 10 is shown in FIG. 1, which includes Schottky diodes 12 and 14 connected to inputs A and B respectively. The anodes of the Schottky diodes are connected to the base of a bipolar transistor 16. A voltage source Vcc is coupled to the anodes of the Schottky diodes via resistor R1 and coupled to the collector of transistor 16 via resistor R2 to provide a bias voltage.
The NAND gate of FIG. 1 is commonly used in a programmable logic array or in a logic circuit as a single logic building block unit, with input nodes shown as A and B and an output node shown as output 18. The input and output nodes are connected to respective nodes of identical logic gates or different logic gates. Such a logic unit has certain drawbacks that are avoided by the present invention.
A top down view of a silicon wafer incorporating the Schottky diodes and bipolar transistor in FIG. 1 is shown in FIG. 2. An N+ cathode contact 20 for Schottky diode 12 forms input A of FIG. 1. Cathode 20 makes ohmic contact with an N-well 22. The anode 24 of diode 12 may be formed of a metal layer, typically platinum silicide or aluminum. The metal in contact with the N-well forms the Schottky diode. The diode 12 is isolated from other components by an isolation region 26, which may be an oxide filled trench, a P-well, or other type of isolation structure.
Schottky diode 14 is formed in the identical manner and is isolated from Schottky diode 12.
The NPN bipolar transistor 16 includes a P-well 30 formed in an N-well 32. A P+ base contact 34 and an N+ emitter 36 are formed in the P-well 30. An N+ collector contact region 38 is the output terminal of the NAND gate.
The resistors R1 and R2 and the connections, such as a metallization layer, are not shown for simplicity.
The circuit shown in FIG. 2 requires a relatively large area due to the isolation of the various structures.
FIG. 3 illustrates one type of logic circuit that may be built using the NAND gate logic units of FIG. 1. One of the NAND gate 10 logic units is shown within dashed outline in FIG. 3.
What is needed is a logic gate structure that uses less area than the prior art, thus allowing a higher density of logic gates in a silicon wafer with increased switching speed.